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Specifications of Common Expansion Board Interface for Renesas Starter Kits

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WHAT'S NEW

20 July 2010

USB Host Stack for Renesas Starter Kit+ for SH7670: New

FAQ: Updated
· New Released.
FAQ NO: 1000132
·Suitable products are updated.
FAQ NO: 107234
FAQ NO: 107235
FAQ NO: 107237
FAQ NO: 107238
FAQ NO: 107239
FAQ NO: 107240
FAQ NO: 107241
·Question and suitable products are updated.
FAQ NO: 107236
·Answer and suitable products are updated.
FAQ NO: 107380

For update history information, please refer to Latest Updates.

Specifications of Common Expansion Board Interface for Renesas Starter Kits

Through-holes JA1 to JA6 of a CPU board of a Renesas Starter Kit are for use with the common expansion board interface.

JA1, 2: Supported by all Renesas Starter Kits.
JA3: Only on MCUs that support external bus expansion.
JA4: Only on MCUs that support LCD drive control.
JA5, 6: Only on 120 mm x 100 mm boards.

Note:
Depending on the Renesas Starter Kit, common expansion board interface functions may not be supported, or may not be able to be used simultaneously with expansion board interface functions. Please refer to the user's manual of your Renesas Starter Kit for details.

For CPU board dimensions, please refer to the following PDF file.
Renesas Starter Kit CPU Board Size (29KB)

Click an expansion interface (gray block) in the graphic to jump to a pin table.
block diagram

JA1 Expansion board interface June 16, 2010

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	5V Power supply	5V	-	2	GND	GND	-
3	3.3V Power supply	3V3	-	4	GND	GND	-
5	Analog power supply	AVCC	-	6	Analog GND	AVSS	-
7	Analog reference voltage	VREF	-	8	A/D trigger	ADTRG	I
9	A/D converter	ADC0	I	10	A/D converter	ADC1	I
11	A/D converter	ADC2	I	12	A/D converter	ADC3	I
13	D/A converter	DAC0	O	14	D/A converter	DAC1	O
15	I/O ports	IO_0	I/O	16	I/O ports	IO_1	I/O
17	I/O ports	IO_2	I/O	18	I/O ports	IO_3	I/O
19	I/O ports	IO_4	I/O	20	I/O ports	IO_5	I/O
21	I/O ports	IO_6	I/O	22	I/O ports	IO_7	I/O
23	External interrupt request	IRQ3	I	24	I²C-bus spare port	IIC_EX	-
23	M2_HSIN0	M2_HSIN0	I	24	I²C-bus spare port	IIC_EX	-
25	I²C-bus data transmit/receive	IIC_SDA	I/O	26	I²C-bus clock	IIC_SCL	I/O

JA2 Expansion board interface June 16, 2010

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	Reset	RESET	I	2	External clock input	EXTAL	I
3	Non-Maskable interrupt request	NMI	I	4	GND	GND	-
5	WDT Overflow	WDT_OVF	O	6	Serial port transmit	SCIaTX	O
7	External interrupt request	IRQ0	I	8	Serial port receive	SCIaRX	I
7	M1_HSIN0	M1_HSIN0	I	8	Serial port receive	SCIaRX	I
9	External interrupt request	IRQ1	I	10	Serial port clock	SCIaCK	I/O
9	M1_HSIN1	M1_HSIN1	I	10	Serial port clock	SCIaCK	I/O
11	Motor control 1 Up/Down count	M1_UD	I	12	Serial port handshake	CTSRTS	I/O
13	Motor control 1 three-phase PWM output 1 positive	M1_Up	O	14	Motor control 1 three-phase PWM output 1 negative	M1_Un	O
15	Motor control 1 three-phase PWM output 2 positive	M1_Vp	O	16	Motor control 1 three-phase PWM output 2 negative	M1_Vn	O
17	Motor control 1 three-phase PWM output 3 positive	M1_Wp	O	18	Motor control 1 three-phase PWM output 3 negative	M1_Wn	O
19	Timer output	TMR0	O	20	Timer output	TMR1	O
21	Timer input	TRIGa	I	22	Timer input	TRIGb	I
23	External interrupt request	IRQ2	I	24	Motor control 1 POE	M1_POE	I
	Reset on Index (Motor Control)	M1_EncZ	I
	M1_HSIN2	M1_HSIN2	I
25	Motor Control 1 TRCCLK	M1_TRCCLK	I	26	Motor Control 1 TRDCLK	M1_TRDCLK	I

JA3 Expansion board interface (Optional Bus header) June 16, 2010

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	Address signal	A0	O	2	Address signal	A1	O
3	Address signal	A2	O	4	Address signal	A3	O
5	Address signal	A4	O	6	Address signal	A5	O
7	Address signal	A6	O	8	Address signal	A7	O
9	Address signal	A8	O	10	Address signal	A9	O
11	Address signal	A10	O	12	Address signal	A11	O
13	Address signal	A12	O	14	Address signal	A13	O
15	Address signal	A14	O	16	Address signal	A15	O
17	Data signal	D0	I/O	18	Data signal	D1	I/O
19	Data signal	D2	I/O	20	Data signal	D3	I/O
21	Data signal	D4	I/O	22	Data signal	D5	I/O
23	Data signal	D6	I/O	24	Data signal	D7	I/O
25	Data read	RDn	O	26	Data write	WRn	O
25	Data read	RDn	O	26	SDRAM Write Enable	WEn	O
27	Chip select	CSa	O	28	Chip select	CSb	O
29	Data signal	D8	I/O	30	Data signal	D9	I/O
31	Data signal	D10	I/O	32	Data signal	D11	I/O
33	Data signal	D12	I/O	34	Data signal	D13	I/O
35	Data signal	D14	I/O	36	Data signal	D15	I/O
37	Address signal	A16	O	38	Address signal	A17	O
39	Address signal	A18	O	40	Address signal	A19	O
39	Address signal	A18	O	40	SDRAM Bank 0	B0	O
41	Address signal	A20	O	42	Address signal	A21	O
41	SDRAM Bank 1	B1	O	42	SDRAM Bank 2	B2	O
43	Address signal	A22	O	44	Clock output	SDCLK	O
43	SDRAM Bank 3	B3	O	44	Clock output	SDCLK	O
45	Chip select	CSc	O	46	Address line enable	ALE	O
45	Wait	Wait	O	46	SDRAM SDCLK Enable	CKE	O
47	Higher-order byte data write	HWRn	O	48	Lower-order byte data write	LWRn	O
47	SDRAM Data Mask Enable	DQM1	O	48	SDRAM Data Mask Enable	DQM0	O
49	Column address select	CAS	O	50	Row address select	RAS	O

JA4 Expansion board interface (LCD interface) June 16, 2010

If JA4 is used as interface to a built-in LCD segment controller, then the pin assignment shall be:

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	LCD power supply	V1	-	2	LCD power supply	V2	-
3	LCD power supply	V3	-	4	LCD power supply	V4	-
5	GND	Vss	-	6	GND	Vss	-
7	LCD common	COM1	O	8	LCD common	COM2	O
9	LCD common	COM3	O	10	LCD common	COM4	O
11	LCD segment	SEG1	O	12	LCD segment	SEG2	O
13	LCD segment	SEG3	O	14	LCD segment	SEG4	O
15	LCD segment	SEG5	O	16	LCD segment	SEG6	O
17	LCD segment	SEG7	O	18	LCD segment	SEG8	O
19	LCD segment	SEG9	O	20	LCD segment	SEG10	O
21	LCD segment	SEG11	O	22	LCD segment	SEG12	O
23	LCD segment	SEG13	O	24	LCD segment	SEG14	O
25	LCD segment	SEG15	O	26	LCD segment	SEG16	O
27	LCD segment	SEG17	O	28	LCD segment	SEG18	O
29	LCD segment	SEG19	O	30	LCD segment	SEG20	O
31	LCD segment	SEG21	O	32	LCD segment	SEG22	O
33	LCD segment	SEG23	O	34	LCD segment	SEG24	O
35	LCD segment	SEG25	O	36	LCD segment	SEG26	O
37	LCD segment	SEG27	O	38	LCD segment	SEG28	O
39	LCD segment	SEG29	O	40	LCD segment	SEG30	O
41	LCD segment	SEG31	O	42	LCD segment	SEG32	O
43	LCD segment	SEG33	O	44	LCD segment	SEG34	O
45	LCD segment	SEG35	O	46	LCD segment	SEG36	O
47	LCD segment	SEG37	O	48	LCD segment	SEG38	O
49	LCD segment	SEG39	O	50	LCD segment	SEG40	O

JA4 Expansion board interface (Direct LCD Drive) June 16, 2010

If JA4 shall be used for LCD direct drive, the pin assignment shall be:

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	5V Power supply	5V	-	2	5V Power supply	5V	-
3	3.3V Board Power supply	Board_VCC	-	4	3.3V Board Power supply	Board_VCC	-
5	Reserved	-	-	6	Reserved	-	-
7	B1	B1	O	8	B2	B2	O
9	B3	B3	O	10	B4	B4	O
11	B5	B5	O	12	G0	G0	O
13	G1	G1	O	14	G2	G2	O
15	G3	G3	O	16	G4	G4	O
17	G5	G5	O	18	R1	R1	O
19	R2	R2	O	20	R3	R3	O
21	R4	R4	O	22	R5	R5	O
23	ExDMAC ACK EDACK	EDACK	O	24	H-SYNC	HSYNC	O
25	Dot clock	DOTCLK	O	26	LCD_DEN	LCD_DEN	O
27	V-SYNC	VSYNC	O	28	ExDAMC REQ EDREQ	EDREQ	O
29	Sync serial clock	SSCK	O	30	Sync serial input	SSI	I
31	Sync serial output	SSO	O	32	Chip select (active on low)	CSn	O
33	Reset (active on low)	RESn	I	34	GND	GND	-
35	Backlight	BACKLIGHT	O	36	SD dot clock	SD-DOT_CLK	O
37	GND	GND	-	38	GND	GND	-
39	GND	GND	-	40	GND	GND	-
41	Touch panel X drive	X_DRIVE	O	42	Touch panel Y drive	Y_DRIVE	O
43	Touch panel X input 1	X_INPUT1	I	44	Touch panel Y input 1	Y_INPUT1	I
45	Touch panel X input 2	X_INPUT2	I	46	Touch panel Y input 2	Y_INPUT2	I
47	Reserved	-	-	48	Reserved	-	-
49	Reserved	-	-	50	Reserved	-	-

JA5 Expansion board interface June 16, 2010

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	A/D converter	ADC4	I	2	A/D converter	ADC5	I
3	A/D converter	ADC6	I	4	A/D converter	ADC7	I
5	CAN data transmit	CAN1TX	O	6	CAN data receive	CAN1RX	I
7	CAN data transmit	CAN2TX	O	8	CAN data receive	CAN2RX	I
9	External interrupt request	IRQ4	I	10	External interrupt request	IRQ5	I
	Reset on Index	M2_EncZ	I		M2_HSIN2	M2_HSIN2	I
	M2_HSIN1	M2_HSIN1	I		M2_HSIN2	M2_HSIN2	I
11	Motor control 2 Up/Down count	M2_UD	I	12	Motor control 2 Uin	M2_Uin	I
13	Motor control 2 Vin	M2_Vin	I	14	Motor control 2 Win	M2_Win	I
15	Motor control 2 toggle	M2_Toggle	I	16	Motor control 2 POE	M2_POE	I
17	Motor control 2 external input clock	M2_TRCCLK	I	18	Motor control 2 external input clock	M2_TRDCLK	I
19	Motor control 2 three-phase PWM output 1 positive	M2_Up	O	20	Motor control 2 three-phase PWM output 1 negative	M2_Un	O
21	Motor control 2 three-phase PWM output 2 positive	M2_Vp	O	22	Motor control 2 three-phase PWM output 2 negative	M2_Vn	O
23	Motor control 2 three-phase PWM output 3 positive	M2_Wp	O	24	Motor control 2 three-phase PWM output 3 negative	M2_Wn	O

JA6 Expansion board interface June 16, 2010

Pin	Function	Signal	I/O	Pin	Function	Signal	I/O
1	DMA transfer request output	DREQ	O	2	DMA transfer discernment signal input	DACK	I
3	DMA transfer end signal input	TEND	I	4	DMA Standby input	STBYn	I
5	UART transmit	RS232TX	O	6	UART receive	RS232RX	I
7	Serial port receive	SCIbRX	I	8	Serial port transmit	SCIbTX	O
9	Serial port transmit	SCIcTX	O	10	Serial port clock	SCIbCK	I/O
11	Serial port clock	SCIcCK	I/O	12	Serial port receive	SCIcRX	I
13	Motor control 1 toggle	M1_Toggle	I	14	Motor control 1 Uin	M1_Uin	I
15	Motor control 1 Vin	M1_Vin	I	16	Motor control 1 Win	M1_Win	I
17	Reserved	-	-	18	Reserved	-	-
19	Reserved	-	-	20	Reserved	-	-
21	Reserved	-	-	22	Reserved	-	-
23	Unregulated supply	Unregulated_VCC	-	24	GND	GND	-