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SiP (System-in-Package) Technology

Noise-reduction and Cost-saving Benefits Give SiP Technology a Growing Role in New Semiconductor Devices

Renesas is strengthening an integrated development infrastructure that includes SoC development and takes maximum advantage of the benefits of SiP technology.

The demand for SiP (System-in-Package) technology in the development of sophisticated electronic products is growing strongly and Renesas shipped approximately 100 million SiP devices in the first half of 2008 alone. Besides the well-known advantages of smaller size, slimmer profile, and lighter weight, SiP ICs offer other important benefits, including superior noise characteristics, high-speed bus design, cost savings, faster development times, and security. As a result, a rapidly increasing number and diversity of products today incorporate SiP solutions. Addressing this economic opportunity and market imperative, we now have a development and design infrastructure covering everything from design and testing through to chip mounting. Further, Renesas is meeting the wide span of customer needs through the development of SoCs (System-on-Chip devices) created specifically for integration into SiP devices and then installed into optimized SiP solutions using our world-class assembly and packaging technology.

Evolving a role change: from SiPs as SoC alternatives to SoCs as SiP components

A SiP (System in Package) device (sometimes also called “Solution Integrated Product?” by Renesas) integrates a system solution consisting of a number of semiconductor chips into a single package. Years ago, SiP technology merely encompassed techniques for combining separate existing semiconductor chips such as microcomputers, memory, and analog ICs into a single package. Such SiPs became successful design solutions for certain types of products because they allowed designs to be made thinner and smaller.

The alternative technology for creating SiP system solutions was then, and still is today, to develop an application-specific LSI, thereby allowing the production of an SoC (System-on-Chip) single-chip solution. SoC solutions can be less expensive than SiPs in high volumes, but they involve much higher R&D costs and longer development times. Other SoC shortcomings include semiconductor manufacturing process limitations that affect the type and/or performance of on-chip functions. Many engineers consider a SiP to be an SoC alternative that is primarily used in cases where it would be difficult to develop a standalone SoC. That perception is now outdated

When one thinks about the types of products that use SiPs, the usual impression is that they are found mainly in small devices such as mobile phones, digital still cameras (DSCs), and digital video cameras (DVCs). This opinion is also outdated. Applications for SiP solutions have broadened greatly in recent times and the number of products that use this versatile technology is growing rapidly (see Figure 1). Today, due to the advantages that SiPs offer and the increasing importance of the benefits they provide, SiP solutions are increasingly being adopted in comparatively larger devices that are not subject to particularly strong constraints on the space available for components. Especially, there has been a rapid growth in customers using in SiPs in high-volume products such as freestanding digital TVs, printers, and optical disk drives.

Beyond offering the attractive characteristics of small size and light weight, SiPs are gaining favor with system engineers by satisfying new requirements, such lower EMI noise, ease of high-speed bus design, and security features. Significantly, SiP solutions are also acknowledged to be a good way to achieve better control of product costs through lower total costs, lower development costs, shorter development times, and simplified component procurement. Indeed, the increased competitiveness of these design solutions has created an economic opportunity and market imperative for Renesas, since we have long been an industry leader in SiP technology.

One result of the situation today is that the SIP solutions we supply are becoming more sophisticated and capable. Fewer and fewer of them are of the type that combines existing semiconductor chips. Instead, a rapidly growing number of our latest SiP products integrate newly designed SoCs optimized for use in SiPs. Obviously, this is a major shift in our semiconductor R&D activities. The practice of specifying a new chip specifically for ultimate incorporation it into a SiP is become standard. With SoC and SiP products being developed concurrently, we have increased our ability to produce new SiP solutions with greater capabilities and enhanced features, thereby responding better to customers' requirements.

Figure 1: Uses and advantages of SiP technology.
It's becoming more common to find SiP devices in equipment with high-level demands for requirements such as reduced EMI noise, easier high-speed bus design, and security.

Shipping over 100 million SiP devices in six months, most of which combine an SoC with DRAM

Renesas SiP products are being used in a wide range of different types and models of electronic equipment. Our success is evident in the growth of our SiP shipments, which were approximately 100 million in all of 2006 year, and then roughly about the same number of units in just the first half of 2008.

These products can be broadly divided into two categories. One is stacked SiPs, in which the chips are placed on top of each other. This arrangement is sometimes referred to as a three-dimensional IC (3D IC). The other category is planar SiPs, devices in which the chips are laid out horizontally.

Stacked SiPs are particularly effective for achieving miniaturization and increasing component density. By contrast, planar SiPs help meet design requirements such as lower noise, ease of high-speed bus design, high reliability, high heat dissipation, and security. In terms of the external package dimensions, most SiPs smaller than 15mm square are stacked types, whereas those 16mm square or larger are mostly planar types (see Figure 2).

In terms of the combination of chips installed in the latest SiP solutions, an increasing proportion of them contain an SoC and DRAM. A main reason for this is that the memory capacities of DRAM chips are getting larger and manufacturing costs make it difficult to integrate DRAM into the SoC device itself. Another reason is that the speed of the DRAM I/O bus is rising due to faster SoC and microcomputer processing speeds, making it more difficult to properly design the wiring connections between the SoC and DRAM.

Figure 2: Relationship between SiP external dimensions, structure and DRAM capacity.
SiP packages with external dimensions of 15mm square or smaller use the stacked structure, while those 16mm square or larger use a planar structure. A growing proportion of SiP devices combine an SoC or microcomputer chip with DRAM.

Establishing a comprehensive design infrastructure for new SiP products and implementing flexible SoC design using the DFS methodology

Two key features distinguish the SiP design practices Renesas uses. First, we have established a comprehensive design infrastructure covering everything from system design to testing. Second, we've instituted a management procedure that ensures that designs for new SoC devices take into account the requirements of future SiP products.

Our comprehensive design infrastructure starts by partitioning the overall system to identify the blocks that will be integrated on a SiP. Various floor plans for these blocks that satisfy the design requirements are considered, and then either a planar or stacked layout is prepared. Next, test design, substrate design, and functional verification are performed for the SiP. Finally, the design database and an integrated design environment are used to create a SiP with the optimum configuration (see Figure 3).

Designing SoCs using a methodology that takes account of SiP requirements is referred to as "Design for SiP" (DFS). If DFS is used for a SiP in which the SoC and memory are laid out horizontally, for example, the I/O pads in the SoC are positioned in such a way that the wiring connections between the SoC and memory are parallel and as short as possible. Because the DRAMs used are essentially standard commercial models, their I/O pad locations cannot be changed. Accordingly, the pad locations on the SoC must be adjusted to suit the specific memory chip. Doing so reduces the number of wiring layers on the SiP substrate and lowers its cost.

In the case of a stacked SiP in which an SoC chip is right on top of or immediately below an existing semiconductor chip, a spacer may be needed between the adjacent surfaces of the two devices if the pads on one of them interfere with those on the other. In this situation, changing the shape of the SoC chip so that its I/O pads do not overlap vertically with the pads of that neighboring device can eliminate the need for spacers and reduces the cost of the SiP.

On some SiPs that combine an SoC with memory, Renesas integrates the memory BIST (Built-in Self Test) circuit into the SoC device (see Figure 4), an approach that reduces pin count of the SiP because pins are no longer needed for the memory test function. This device design approach is unusual because memory chip manufacturers generally don't release much information about test circuits. However, Renesas benefits from having developed a strong relationship of trust with them.

Figure 3: SiP design process used by Renesas.
Our comprehensive design infrastructure (full-time organization) covers everything from system design through to SiP design, testing, and full-scale production.

Figure 4: Example of how SoC design takes into account SiP requirements.
The SiP doesn't need external test pins because the SoC contains a memory test circuit that provides a dedicated BIST function.

Managing the rapid evolution of SiP development technology, including possible future advances such as through-silicon electrodes

In the area of technology for mounting the chips contained in SiP solutions, we apply the advances produced by the world-class research of the Renesas Group as soon as new techniques are developed and tested. For stacked SiPs, our portfolio of individual technologies now includes low-mold technology with a mounting height of 1.5mm or less and methods for thinly machining the wafer underside with low stress (thicknesses of 70μm are used in full-scale production). We also apply technology for wire bonding with a pitch of only 30μm, flip-chip connection technology that can produce more than 700 pins with a pitch of 40μm or less, and technology for producing ultra-thin 0.2mm SiP substrates (see Figure 5).

Renesas SiP solutions have been through many cycles of improvement thanks to the development of these technologies, among others. For example, the thickness of stacked SiPs in 2005 was approximately 1.7mm for a five-layer stack (five semiconductor chips stacked on top of each other, currently the largest number of layers in full scale production) and about 1.5mm for a two-layer stack. Three years later, in 2008, these thicknesses were reduced to a little over 1.5mm and 1.0mm respectively. By 2010, the thickness of five-layer stacks is expected to fall below 1.5mm, while that of two-layer stacks will drop to about 0.9mm.

Another anticipated development that will provide the ultimate in miniaturization and thinness is the through-silicon electrode technique that we are currently developing jointly with Hitachi. This technology involves making holes in the silicon wafer and forming electrodes between the upper and lower surfaces (see Figure 6). When it can be brought into practical use, the through-silicon electrode technology alone will reduce the height of SiP packages by more than half.

By making ongoing improvements to our SiP development technology, Renesas intends to continue supplying system solutions in packages that are ideally suited to the diverse needs and applications of our customers.

For more information on SiP technology, click here.

Figure 5: SiP structure and roadmap.
Moving beyond stacked and planar configurations, new types of structure include low-cost structures using QFP packaging and structures that separate different functions using PoP techniques. Future developments are expected to include SiPs with ultra-small, very dense structures and constructions that combine excellent heat dissipation and high reliability.

Figure 6: Technologies used in stacked SiPs.
The latest techniques are applied from many fields, including molding, wafer machining, wire bonding, substrates, and flip-chip assembly. Of these, the through-silicon electrode technology now in development appears to have great potential for use in future SiP devices.


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