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Items
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Specifications
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LSI
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Operating frequency: 200 MHz
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Performance:
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Voltage: 1.5 V (internal), 3.3 V (I/O)
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Superscalar architecture: Parallel execution of two instructions
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Packages: 256-pin BGA
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External buses
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Separate 26-bit address and 32-bit data buses
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External bus frequency: 67MHz
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Choice of MFI mode or LCD mode:
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MFI mode: 8-/16-bit parallel interface
(supports 68-/80-family interface)
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LCD mode: LCD controller/data output
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CPU
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Original Renesas SuperH architecture
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32-bit internal data bus
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General register file:
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Sixteen 32-bit general registers (and eight 32-bit shadow registers)
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Seven 32-bit control registers
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Four 32-bit system registers
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RISC-type instruction set (upward-compatible with SuperH Series)
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Fixed 16-bit instruction length for improved code efficiency
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Load-store architecture
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Delayed branch instructions
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Conditional execution
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C-based instruction set
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Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
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Instruction execution time: Maximum 2 instructions/cycle
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Virtual address space: 4 Gbytes (448-Mbyte external memory space)
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Space identifier ASIDs: 8 bits, 256 virtual address spaces
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On-chip multiplier
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Five-stage pipeline
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FPU
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On-chip floating-point coprocessor
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Supports single-precision (32 bits) and double-precision (64 bits)
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Supports IEEE754-compliant data types and exceptions
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Two rounding modes: Round to Nearest and Round to Zero
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Handling of denormalized numbers: Truncation to zero or interrupt generation
for compliance with IEEE754
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Floating-point registers: 32 bits x 16 words x 2 banks
(single-precision x
16 words or double-precision x8 words) x 2 banks
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32-bit CPU-FPU floating-point communication register (FPUL)
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Supports FMAC (multiply-and-accumulate) instruction
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Supports FDIV (divide) and FSQRT (square root) instructions
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Supports FLDI0/FLDI1 (load constant 0/1) instructions
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Instruction execution times
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Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8 cycles
(double-precision)
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Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles
(double-precision)
Note: FMAC is supported for single-precision only.
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3-D graphics instructions (single-precision only):
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4-dimensional vector conversion and matrix operations (FTRV): 4 cycles
(pitch), 7 cycles (latency)
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4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles (latency)
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Five-stage pipeline
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Clock pulse generator (CPG)
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Choice of main clock
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Clock modes:
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CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
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Power-down modes
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Sleep mode
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Deep sleep mode
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Standby mode
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Hardware standby mode
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Module standby mode
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Single-channel watchdog timer
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Memory management unit (MMU)
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4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
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Single virtual mode and multiple virtual memory mode
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Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
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4-entry fully-associative TLB for instructions
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64-entry fully-associative TLB for instructions and operands
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Supports software-controlled replacement and random-counter replacement
algorithm
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TLB contents can be accessed directly by address mapping
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Cache memory
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Instruction cache (IC)
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16 kbytes, 2-way set associative
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256 entries, 32-byte block length
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Cache-double-mode (16-kbyte cache)
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Index mode
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Operand cache (OC)
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32 kbytes, 2-way set associative (LRU)
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512 entries, 32-byte block length
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Cache-double-mode (32-kbyte cache)
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Index mode
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RAM mode (16-kbyte cache + 16-kbyte RAM)
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Choice of write method (copy-back or write-through)
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Single-stage copy-back buffer, single-stage write-through buffer
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Cache memory contents can be accessed directly by address mapping
(usable
as on-chip memory)
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Store queue (32 bytes x 2 entries)
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Interrupt controller (INTC)
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Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to IRQ4
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15-level signed external interrupts: IRL3 to IRL0
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On-chip peripheral module interrupts: Priority level can be set for each module
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User break controller (UBC)
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Supports debugging by means of user break interrupts
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Two break channels
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Address, data value, access type, and data size can all be set as break
conditions
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Supports sequential break function
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Bus state controller (BSC)
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Supports external memory access
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External memory space divided into seven areas, each of up to 64 Mbytes, with
the following parameters settable for each area:
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Bus size (8, 16, or 32 bits)
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Number of wait cycles (hardware wait function also supported)
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SRAM, synchronous DRAM, or burst ROM
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Supports PCMCIA interface (only in little endian mode)
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Synchronous DRAM refresh functions
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Programmable refresh interval
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Supports auto refresh mode and self-refresh mode
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Synchronous DRAM burst access function
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Big endian or little endian mode can be set
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Direct memory access controller (DMAC)
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8-channel physical address DMA controller
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Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
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Address modes:
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1-bus-cycle single address mode
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2-bus-cycle dual address mode
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Transfer requests: External, peripheral module, or auto-requests
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Choice of DACK or DRAK (four external pins)
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Bus modes: Cycle-steal or burst mode
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Supports on-chip FIFO bridge (16-stage x 32-bit FIFO x 7) to achieve
high-speed transfer for HAC/SSI, USB and LCDC
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Timer unit (TMU)
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3-channel auto-reload 32-bit timer
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Input-capture function (only channel 2)
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Choice of six types counter input clocks (external and peripheral clocks)
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Compare match timer (CMT)
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4-channel auto-reload 32-bit timers
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Choice of 16 or 32 bits
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Choice of 1-shot or free-running operation
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Choice of an interrupt source or DMA transfer request from compare match or
overflow
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Serial communication interface (SCIF)
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Three full-duplex communication channels
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On-chip 128-byte FIFOs for all channels
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Choice of asynchronous mode or synchronous mode
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Can select any bit rate generated by on-chip baud-rate generator
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On-chip modem control function (SCIF_RTS and SCIF_CTS) for channel 1 and 2
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Audio codec interface (HAC)
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Digital interface for audio codec
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Supports transfer for slot 1 to slot 4
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Choice of 16- or 20-bit DMA transfer
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Supports various sampling rates by adjusting slot data
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Generates interrupt: data ready, data request, overflow, and underrun
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Serial sound interface (SSI)
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2-channel bi-directional transfer (maximum)
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Support multi-channel and compressed-data transfer
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Selectable frame size
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I2C bus interface (I2C)
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2 channels (maximum)
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Master/slave
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16-byte FIFO
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Supports high-speed mode (400 kbits/sec)
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Supports version 1.0
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Multimedia card interface (MMCIF)
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Supports MMC mode
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A maximum bit rate of 20 Mbps at 20 MHz of peripheral clock
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Interface with MCCLK output for transfer clock output, MCCMD I/O for command
output/response input, MCDAT I/O (data I/O)
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Four interrupt sources
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Smart card interface (SIM)
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Supports ISO/IEC7816-3 (Identification card)
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Asynchronous half-duplex transfer (8 bits)
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Can select any bit rate generated by on-chip baud-rate generator
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Generates and checks parity bit
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Four interrupt sources
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Controller area network 2 (HCAN2)
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2 channels (maximum)
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Supports CAN specification 2.0A and 2.0B
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Standard data and remote frame (11-bit ID)
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Extended data and remote frame (29-bit ID)
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32 independent message buffers using standard (11-bit) and extended (29-bit)
ID format
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31 Mailboxes can be used for transmission or reception
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One Mailbox can be used for only reception
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Message reception filtering by IDs:
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Standard message ID
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Extended message ID
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Local reception filter for reception-only Mailbox (standard and extended
message ID) can be specified
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Power-down sleep mode
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A maximum of 1-Mbit/s CAN data transfer rate can be specified
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Transmit message queue having internal priority sorting mechanism which handle
priority-inversion issue of real time applications
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Data buffer access without hand-shaking
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Serial peripheral interface (HSPI)
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1 channel
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Master/slave mode
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Selectable bit rate generated by on-chip baud-rate generator
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Multifunctional interface (MFI)
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2-kbyte internal memory can be read from or written to via the MFI pin in
32-bit units or by the CPU in 8-/16-/32-bit units.
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Choice of 8- or 16-bit parallel interface
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Supports 68-/80-family interface (can be switched during reset)
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Endians can be switched
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USB host
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1 channel
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Supports USB version 1.1 and OHCI 1.0
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Supports data transfer rate of 1.5 Mbps and 12Mbps
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On-chip 8-kbyte SRAM as shared memory defined in OHCI specification
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LCD controller (LCDC)
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Supports 16 x 1 to 1024 x 1024 dots (8 bpp: a maximum of 640 x 480 dots, 16
bpp: a maximum of 320 x 240 dots)
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Supports 4, 8, 15, and 16 bpp color modes
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Supports 1, 2, 4, and 6 bpp grayscale modes.
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Supports TFT/DSTN/STN display
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Selectable signal polarities
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24-bit color palette memory (16 bits of 24 bits are valid: R: 5/G: 6/B: 5)
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Unified graphics memory architecture
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A/D converter (ADC)
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10-bit resolution
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4-channel input
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Three types of conversion modes
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Single mode: 1-channel A/D conversion
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Multi mode: 1- to 4-channel A/D conversion
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Scan mode: 1- to 4-channel A/D conversion
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Conversion time: 8 s for are channel (maximum)
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Absolute error plus or minus 4LSB
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General I/O (GPIO)
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70 general I/O port (69 for I/O and one for output)
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